Phase change random access memories (PRAMS) are non-volatile memory devices that store data using a phase change material, e.g., Ge—Sb—Te (GST). The phase change material, which exhibits different resistive values depending on the crystalline or amorphous phase thereof, is programmed by thermal treatment to set the phase of the material.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to as a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by joule heating of the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time. In each case, the material is allowed to cool to its original temperature after the heat treatment. Generally, however, the cooling occurs much more rapidly when the phase-change material is reset to its amorphous state.
In a read operation, a given read current is provided to a selected memory cell, and the “1” or “0” resistive state of the memory cell is discriminated using a sense amplifier based on a voltage of the cell.
In order to increase the capacity and integration density of phase change memory devices, the phase-change memory devices may be implemented as a hierarchical bit line structure having a global bit line and a plurality of local bit lines. In this case, there is a difference in physical length between phase-change memory cells coupled to local bit lines located farther away from a write circuit and/or a read circuit and phase-change memory cells coupled to local bit lines located near the write circuit and/or read circuit. Thus, noting that a parasitic resistance is present in a global bit line, the resistance of a path extending from a write circuit and/or a read circuit to a selected memory cell varies depending on the position of the selected phase-change memory cell.
Thus, due to the resistance variations, a smaller amount of write or read current is applied to a phase-change memory cell coupled to a local bit line located farther from a write and/or read circuit than a phase-change memory cell coupled to a local bit line located closer to the write and/or read circuit. These variations in read and/or write currents can result in read and/or write failures.